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Research Article | Open Access
Volume 13 2021 | None
HIGH-SPEED, LOW-POWER FULL ADDER DESIGN USING MUX IN 16NM CMOS TECHNOLOGY
JAYA BANGARI, S VAISHALI, BHARATHA SATHEESH, GARRE MOUNIKA, JANGAM HARIKA
Pages: 3755-3762
Abstract
This project proposes new circuits for simultaneous XOR–XNOR and XOR/XNOR operations. The low output capacitance and low short-circuit power dissipation of the suggested circuits result in highly optimised power usage and delay. Additionally, we suggest six brand-new hybrid 1-bit full-adder (FA) circuits that are built on the innovative full-swing XOR–XNOR or XOR/XNOR gates. Regarding speed, power consumption, power delay product (PDP), driving capability, and other factors, each of the suggested circuits has advantages of its own. Comprehensive HSPICE and Cadence Virtuoso simulations are run to examine the performance of the suggested designs. The suggested solutions outperform previous FA designs in terms of speed and power, according to the simulation findings, which are based on Tanner's 16-nm CMOS process technology model. A novel approach of transistor sizing is used in order to maximise the circuits' PDP. The suggested approach uses the particle swarm optimisation technique for numerical computing to reach the target value for the optimal PDP with fewer iterations. Variations in the supply and threshold voltages, output capacitance, input noise immunity, and transistor size are examined in the suggested designs.
Keywords
HSPICE, swarm optimization
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