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Research Article | Open Access
Volume 14 2022 | None
Designing an effective Adiabatic Low Power CMOS Logic Circuit for energy efficiency using GDI technique
Nagarjuna Reddy Gujjula , Dr.Rameshbabu.K
Pages: 2918-2927
Abstract
When it comes to the electronics industry, power dissipation and circuit area are the most important considerations.According to previous research, the Full-Swing ADIABATIC GDI Technique has been shown to be an excellent way for low power digital design while also decreasing the circuit space. The proposed ALU architecture contains a 2x1 Multiplexer, 4x1 Multiplexer, and a low-power Full Adder cell for implementing arithmetic and logic operations.Cadence Virtuoso was used to simulate the 65nm TSMC process, which was completed successfully. When compared to earlier studies, the proposed design consumes less power and uses a smaller number of transistors while still attaining full swing function, according to the findings
Keywords
GDI, Multiplier, multiplier register, arithmetic circuit, low power design
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